A 100 KS / s 65 dB DR Σ − ∆ ADC with 0 . 65 V supply voltage
نویسندگان
چکیده
We present a low-power Σ − ∆ modulator to be used in the baseband sections of wireless sensor network receivers with 0.65V Vdd operation. The design is optimized for low-power consumption and low operating supply by minimizing operational amplifier open-loop gain. Simple differential pair amplifiers with ≈ 40dB of open loop gain and low noise factor are employed as the integrator cores and guarantee a spurious-free dynamic range(SFDR) of 63dB. The prototype employs only standard Vth devices and dissipates 27μW to achieve 65dB dynamic range in a 50KHz bandwidth, including regulated bias. The peak SNDR of 59.5dB corresponds to a figure of merit (FOM) of 0.36pJ/Conv.Step.
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